This invention relates to a decoupling capacitive structure (i.e., a structure including one or more capacitors) and electrical components including the capacitive structure, and to production methods thereof.
When designing a package for an integrated circuit chip such as a flip chip or a wire bond chip, a ball grid array (BGA) or other area array or peripheral leaded package is used to allow input/output (I/O) connections to numerous terminals on the chip. The package basically serves as a spatial adaptor between the relatively large terminals on a printed wiring board (PWB) and the much smaller terminals or connection points on the chip itself.
As part of the power delivery system to the chip, one or more decoupling capacitors (also called bypass capacitors) are often used as a charge reservoir such that any sudden requirement for current can be supplied to the chip with the voltage maintained constant or nearly constant. Additionally, the capacitors minimize transient currents in the power supplied to the chip. The capacitors are in parallel with a source supply and its associated load such that transient currents pass through the capacitor and do not reach the load.
With increased switching speeds in chips, such as microprocessor chips, parasitic inductances in the power distribution system become increasingly problematical because, among other things, they impair the performance of decoupling capacitors. The parasitic inductances include inductances in the decoupling capacitors themselves as well as in the circuit paths from the capacitors to the chip. Basically, the connections between any capacitor and the chip introduce additional parasitic inductance beyond the parasitic inductance of the capacitor itself. Capacitors that are distant from the chip do not provide satisfactory decoupling at higher switching speeds. In general, the farther from the chip, the greater the parasitic inductance and the less effective the capacitor in decoupling high frequency transients.
Various techniques have been proposed to place the decoupling capacitors as close as possible to the chip.
One technique has involved putting decoupling capacitors within the chip itself, but that disadvantageously restricts the number of transistors that can be placed in the chip. Additionally, the capacitance values are relatively low.
Another technique uses placement of one or more discrete chip capacitors (typically stacked, co-fired ceramic capacitors) around the periphery of the package to which the chip will be attached. Unfortunately, such capacitors have higher parasitic inductance than desirable. Again, this is especially troublesome when operating at high switching speeds due to reduced decoupling performance. Further, discrete chip capacitors, being relatively thick, require customizing (e.g., milling out cavities to accommodate the capacitors) of a heat sink and/or other component (stiffener or spacer) mounted as part of the top of the package made with the chip and package substrate.
The present invention avoids the stated drawbacks of the various capacitor arrangements discussed.
An object of the present invention is to provide a new and improved capacitive structure useful in a decoupling arrangement for a ball grid array (BGA) or other chip package.
A more specific object of the invention is to provide high capacitance and low parasitic inductance decoupling arrangement for a chip power supply.
Yet another object of the invention is to provide a decoupling arrangement for use with a BGA or other chip package without requiring special milling or other customization of a heat sink or other part mounted on a chip.
Still another object of the invention is to provide methods of making a capacitive structure and devices incorporating the capacitive structure.
The above and other objects of the present invention are realized by building a thin film capacitive structure on thin flexible polymer material and mounting that capacitive structure on otherwise unused portions of the chip package. The thin film capacitive structure has intrinsically high capacitance density and low parasitic inductance.
According to one of its aspects, the present invention may be described as an electrical component including an integrated circuit package having a substrate with a chip side, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate. The chip side of the substrate has a chip area for disposition of a chip and a chip-side remainder area. The opposite side of the substrate has an opposite-side connection area and an opposite-side remainder area. A decoupling structure includes at least a first decoupling capacitor having two different capacitor plates spaced apart with dielectric therebetween. The capacitor plates are films preferably no more than 5 microns in thickness. The capacitor plates are disposed in one of the remainder areas. Preferably, the decoupling structure includes capacitor plates covering at least 70 percent of the one remainder area. The chip area is preferably centrally located on the chip side and the chip-side remainder area extends peripherally around the chip area, and the decoupling structure is disposed in the chip-side remainder area. The two capacitor plates may include one plate that substantially encircles the chip area. The chip side of the substrate may define a plane (i.e., is either a plane or substantially planar with some deviations from a defined plane), with the two capacitor plates being spaced apart in a direction normal to the plane. The aforementioned one plate may cover at least 70 percent of the chip-side remainder area, and the decoupling structure is preferably an applique applied to a surface of the substrate.
The electrical component may further include a chip disposed on the chip area and electrically connected at the connection points, and a heat sink disposed on a side of the chip opposite the substrate, the decoupling structure not requiring any cavities in the heat sink for accommodating the decoupling structure. The decoupling structure may have a thickness less than half the thickness of the chip, which may be a flip chip.
In a preferred form, the decoupling structure provides at least 100 nF of capacitance per square centimeter of area of one of the capacitor plates. The decoupling structure may include a second decoupling capacitor having two capacitor plates spaced apart with dielectric therebetween, one of the capacitor plates of the second decoupling capacitor being a common plate also serving as one of the capacitor plates of the first decoupling capacitor, all of the capacitor plates preferably being thin films with thicknesses of no more than 5 microns, with the dielectric between any two of the capacitor plates being no more than 1 micron in thickness.
According to another of its aspects, the invention may alternately be described as an electrical component including a decoupling structure including first and second metal layers spaced apart with dielectric therebetween so as to define at least a first decoupling capacitor having at least two different plates, at least one of the metal layers substantially surrounding an interior opening through the decoupling structure, the metal layers preferably having thicknesses of no more than 5 microns. The decoupling structure may provide at least 100 nF of capacitance per square centimeter of area of one of the capacitor plates and may also have an equivalent parasitic inductance of less than 20 nH for each capacitor in the decoupling structure. Each of the capacitor plates preferably includes connection locations extending alongside the opening, with the dielectric between any two of the capacitor plates being no more than 1 micron in thickness.
The electrical component may further include an integrated circuit package having a substrate with a chip side, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate, the chip side of the substrate having a chip area for disposition of a chip and a chip-side remainder area. The decoupling structure is attached to the chip-side remainder area, the chip side of the substrate defines a plane, and the two capacitor plates are spaced apart in a direction normal to the plane defined by the chip side. A chip is disposed on the chip area and electrically connected at the connection points. A heat sink is disposed on a side of the chip opposite the substrate, the decoupling structure not requiring any cavities in the heat sink for accommodating the decoupling structure.
The decoupling structure may further include one or more additional decoupling capacitors each having two plates spaced apart, with one of the plates of each additional capacitor being constituted by a portion of a plate that is common to all of the capacitors of the structure.
According to yet another aspect, the present invention may be described as an electrical component including an integrated circuit package having a spatial adaptor substrate with a chip side, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate, the chip side of the substrate defining a plane and having a chip area for disposition of a chip and a chip-side remainder area, the opposite side of the substrate having an opposite-side remainder area. The component has a decoupling structure including at least a first decoupling capacitor having two different plates spaced apart from each other in a direction normal to the plane defined by the chip side with dielectric therebetween, the capacitor plates being disposed in one of the remainder areas and covering at least 70 percent of that remainder area. Preferably, the decoupling structure provides at least 100 nF of capacitance per square centimeter of area of one of the capacitor plates, and the capacitor plates are thin films of thicknesses no greater than 5 microns.
According to still another aspect, the present invention may be described as an electrical component including an integrated circuit package having a substrate with a chip side that defines a plane, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate, the chip side of the substrate having a chip area for disposition of a chip and a chip-side remainder area. A decoupling structure includes at least a first decoupling capacitor having two capacitor plates spaced apart in a direction normal to the plane defined by the chip side, the capacitor plates being disposed in the chip-side remainder area and being thin films of thickness no greater than 5 microns and covering at least 70 percent of the chip-side remainder area. The chip area is preferably centrally located on the chip side with the chip-side remainder area substantially encircling the chip area. The two capacitor plates include a ground plate that extends peripherally completely in a closed loop around the chip area.
According to still another aspect, the present invention may be described as a method of making an electrical component, comprising providing a first capacitor plate layer having a thickness of no more than 5 microns, providing a second capacitor plate layer having a thickness of no more than 5 microns, the second capacitor plate layer being separated from the first capacitor plate by a dielectric to form a capacitive structure, and providing a opening through the capacitive structure such that the first and second capacitor plate layers are disposed in a region substantially encircling the opening. Preferably, the method further includes disposing the capacitive structure on an integrated circuit package having a substrate with a chip side, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate, the chip side of the substrate having a chip area for disposition of a chip and a chip-side remainder area, with the capacitive structure being disposed on the chip-side remainder area with the opening positioned in correspondence with the chip area.
According to still another aspect, the present invention may be described as a method of making an electrical component, comprising providing a first capacitor plate layer having a thickness of no more than 5 microns; providing a second capacitor plate layer having a thickness of no more than 5 microns, the second capacitor plate layer being separated from the first capacitor plate by a dielectric to form a capacitive structure, disposing the capacitive structure on an integrated circuit package having a substrate with a chip side, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate, the chip side of the substrate having a chip area for disposition of a chip and a chip-side remainder area, the opposite side of the substrate having an opposite-side connection area and an opposite-side remainder area, and the capacitive structure being disposed on one of the remainder areas.
According to still another aspect, the invention may be described as a method of making an electrical component, comprising providing a first capacitor plate layer, providing a second capacitor plate layer separated from the first capacitor plate layer by a dielectric to form a capacitive structure, and removing a portion of the capacitive structure to form an opening therethrough such that the first and second capacitor plate layers are disposed in a region substantially surrounding the opening.
According to still another aspect, the invention may be described as an electrical component comprising an integrated circuit package having a substrate with a chip side, an opposite side opposite to the chip side, and connection points for a chip on the chip side of the substrate, the chip side of the substrate having a chip area for disposition of a chip and a chip-side remainder area, the opposite side of the substrate having an opposite-side connection area and an opposite-side remainder area; and a decoupling structure including a thin-film decoupling capacitor disposed on one of the remainder areas.